Cache Hits, Conflict Misses and Reuse

Cache Hits, Conflict Misses and Reuse: experiment guide

This simulation starts with an empty cache and executes a deterministic sequence of block reads. Cache slots controls how many whole blocks fit, from one through eight. Distinct blocks controls the number of unique block addresses per pass, from one through sixteen. Block stride multiplies each index to generate the addresses 0, stride, 2 times stride, and so on. Passes repeats this ordered sequence one through four times. The blocks are abstract identifiers, not byte addresses or tokens. A fixed block size is implicit, and each request is a read of one block. These controls let you separate reuse, capacity pressure and mapping conflicts without inventing nanosecond measurements.

Worked details 1

Mapping selects Direct mapped or Fully associative LRU. Direct mapping places block b in set b modulo the number of cache slots; each set holds exactly one block. A miss replaces that set’s previous occupant. Fully associative mapping uses one set with all slots, allows every block in any slot and evicts the least recently used block when full. Both hits and fills move their block to the most recently used end. The diagram orders fully associative entries from least to most recently used; the table records request number, pass, block, set, hit or miss, evicted block, and cumulative counts. First-ever references are labeled compulsory misses. Later misses are called reuse misses because an exact capacity-versus-conflict classification requires a comparison cache.

Worked details 2

At Reset parameters, four slots receive four distinct blocks at stride one for two passes. Seek to sixty seconds: requests are 0,1,2,3,0,1,2,3, producing four compulsory misses followed by four hits, a hit rate of one half. Change Block stride to four while retaining direct mapping. Addresses become 0,4,8,12 and all map to set zero, so all eight requests miss despite four total slots. Select Fully associative LRU and repeat: the same addresses now produce four misses and four hits. This paired experiment identifies mapping conflicts, because an equal-capacity fully associative cache retains all four blocks. Next set Distinct blocks to five with four slots and fully associative LRU: the cyclic scan produces ten misses, demonstrating a working set that exceeds capacity.

Worked details 3

Play spreads every request evenly across sixty teaching seconds. Pause freezes counters and contents. Restart empties the cache and pauses without changing controls. Speed selects 0.25, 1 or 4 times the presentation rate; Seek reconstructs the exact state at a chosen paused time, including evictions. Reset parameters restores the complete default scenario. Before the first request the hit rate is undefined, rather than a fabricated zero-percent observation. Fractional dimensions and values outside the shown bounds are rejected. The model omits multilevel inclusivity, coherence, writes, replacement approximations, hardware prefetch, nonblocking misses, translation and physical address hashing. In particular, these cache blocks are not a transformer KV cache, whose stored tensors solve a different reuse problem. The linked articles provide that distinction; this simulator does not estimate token throughput or infer where real model weights reside.