CPU SLM Stack: Trace a Dense Kernel

CPU SLM Stack: Trace a Dense Kernel: experiment guide

This CPU stack lesson follows one concrete request, y=Wx, through application inputs, engine work assignment, kernel dot products, logical vector chunks and storage accounting. The arithmetic runs in JavaScript. It does not call BLAS, execute a selected instruction set or benchmark the processor in your browser. The word logical is essential: lane groups and worker slots describe a deterministic partition that can be inspected, not an assertion that the browser launches those threads or uses that SIMD width. The output and every partial product are real calculations, so changing dimensions changes the work rather than merely highlighting a different software layer.

Worked details 1

Input width chooses one through thirty-two coordinates. Coordinate i of the input is i modulo four minus one, producing [-1,0,1,2,-1,...]. Output width chooses one through sixteen rows of W. Weight at row r, column i is (r+i) modulo five minus two, an integer between minus two and two. These small generated fixtures are not trained SLM weights. Their values are exposed in the full-precision inspector. Every row dot product produces one output coordinate. Scalar multiplication count is input width times output width. The mathematical addition count is output width times input width minus one, because a sum of n products needs n minus one additions. This expression count excludes implementation-specific additions to zero.

Worked details 2

Logical lanes selects a chunk width from one through eight. Each row is visited left to right in groups of that width. The final group is clipped to the input width; its unoccupied lanes are counted as tails, never read as extra tensor elements. Each trace entry includes the row, worker, start-inclusive and end-exclusive coordinates, individual products, partial sum and cumulative row sum. Changing the lane width changes chunk count and intermediate sums but preserves the completed output exactly for these integer fixtures. Worker slots assigns row r to slot r modulo the number of slots. The displayed chunk counts show possible imbalance and idle slots. They cannot be converted into a speedup without a scheduling and hardware model.

Worked details 3

Weight storage bits selects either signed eight-bit integers or thirty-two-bit floats. Every fixture weight is exactly representable in both formats, so this particular storage change loses no information. It changes only the weight payload calculation. Inputs and outputs are always counted as four-byte values; arithmetic uses JavaScript numbers in either mode. Payload budget bytes is an explicit integer allowance against which the sum of weight, input and output bytes is compared. Equality fits. One byte below the total fails with an exact deficit. This diagnostic does not prevent the small teaching calculation from executing and does not measure actual browser allocation. Object overhead, stack, engine code, optimizer states, activations beyond this layer, cache lines, alignment, scale metadata and KV cache are excluded.

Worked details 4

At Reset parameters, input width is five, output width three, lanes four, workers two, storage thirty-two bits and budget one hundred bytes. The input is [-1,0,1,2,-1], and the three outputs are [2,8,-1]. There are fifteen multiplications, twelve scalar additions, six logical chunks and nine unused tail lanes. Slot chunk counts are [4,2]. Weight, input and output payloads are sixty, twenty and twelve bytes, totaling ninety-two, so the budget fits. Set budget to ninety-one for a one-byte failure, then ninety-two to test equality. Change weight storage to eight bits to reduce the total to forty-seven bytes without changing any output. Set lanes to one to get fifteen chunks and no tail lanes. Set workers to eight to expose five unused slots.

Worked details 5

Play walks through the five stack views over sixty teaching seconds. Pause stops the inspection clock. Next stage advances one view; Seek pauses at any chosen time; Restart returns to the application view while retaining inputs. Speed offers quarter, normal or four times the teaching rate. Input changes recompute and pause, while Reset parameters also restores the opening fixture. No stage is delayed to imitate a measured instruction or memory access. The table and full-precision inspector supply all numerical alternatives to the diagram. Counts must be whole numbers within the labeled bounds; blank, fractional or out-of-range entries report an error and disable playback. The fixture illustrates abstraction boundaries in one dense operation, and does not claim to implement tokenization, an inference engine or an entire CPU language model.